Verilog Parameters

In Verilog, parameters are constants and do not belong to any other data type such as register or net data types.

A constant expression refers to a constant number or previously defined parameter. We cannot modify parameter values at runtime, but we can modify a parameter value using the defparam statement.

The defparam statement can modify parameters only at the compilation time. Parameter values can be modified using # delay specification with module instantiation.

In Verilog, there are two methods to override a module parameter value during a module instantiation.

By using the defparam keyword.
And module instance parameter value assignment.

After the defparam keyword, the hierarchical path is specified to the parameter and the parameter’s new value. This new value should be a constant expression. If the right-hand side expression references any parameters, it should be declared within the module where defparam is invoked.

The module instance parameter value assignment method seems like an assignment of delay to gate instance. This method overrides parameters inside instantiated modules as they appear in the module. Using this format, parameters cannot be skipped.

Constant expressions can contain previously declared parameters. When changes are detected on the previously declared parameters, all parameters that depend on this value are updated automatically.

Consider, a 4-bit adder can be parameterized to accept a value for the number of bits, and new parameter values can be passed during module instantiation. So, an N-bit adder converts into a 4-bit, 8-bit or 16-bit adder. They are like arguments to a function that is passed during a function call.

  parameter MSB = 7;                  // MSB is a parameter with the constant value 7   parameter REAL = 4.5;               // REAL holds the real number   parameter FIFO_DEPTH = 256,            MAX_WIDTH = 32;           // Declares two parameters  parameter [7:0] f_const = 2’b3;     // 2 bit value is converted into 8 bits; 8’b3   

There are two types of parameters, module and specify, and both accept a range specification. But, they are made as wide as the value to be stored them, and hence a range specification is not necessary.

Module parameters

It can be used to override parameter definitions within a module and makes the module have a different set of parameters at compile time. A parameter can be modified with the defparam statement. It is common to use uppercase letters in names for the parameter to notice them instantly.

The below module uses parameters to specify the bus width, data width and the depth of FIFO within the design, and can be overridden with new values when the module is instantiated or by using defparam statements.

  module design_ip  ( addr, wdata, write, sel, rdata);       parameter  BUS_WIDTH    = 32,                  DATA_WIDTH   = 64,                  FIFO_DEPTH   = 512;       input addr;       input wdata;       input write;       input sel;       output rdata;       wire [BUS_WIDTH-1:0] addr;       wire [DATA_WIDTH-1:0] wdata;       reg  [DATA_WIDTH-1:0] rdata;       reg [7:0] fifo [FIFO_DEPTH];  endmodule  

In the new ANSI style of Verilog port declaration, we may declare parameters such as:

  module design_ip  #(parameter BUS_WIDTH=32,  parameter DATA_WIDTH=64)              (input [BUS_WIDTH-1:0] addr,  // other port declarations     );  

Overriding parameters

Parameters can be overridden with new values during module instantiation. The first part is the module called design_ip by the name d0 where new parameters are passed within # ( ).

The second part is use a Verilog construct called defparam to set the new parameter values. The first method is commonly used to pass new parameters in RTL designs. And the second method is used in testbench simulations to quickly update the design parameters without having to reinstantiate the module.

  module tb;    // Module instantiation override       design_ip  #(BUS_WIDTH = 64, DATA_WIDTH = 128) d0 ( [port list]);  // Use of defparam to override  defparam d0.FIFO_DEPTH = 128;  endmodule  

The module counter has two parameters N and DOWN, which is declared to have a default value of 2 and 0.

N controls the number of bits in the output, effectively controlling the width of the counter. It is a 2-bit counter by default.

Parameter DOWN controls whether the counter should increment or decrement. The counter will decrement because the parameter is set to 0.

2-bit up Counter

  module counter    # ( parameter N = 2, parameter DOWN = 0)      (input clk, input rstn, input en, output reg [N-1:0] out);      always @ (posedge clk) begin      if (!rstn) begin        out <= 0;      end else begin        if (en)          if (DOWN)            out <= out – 1;          else            out <= out + 1;        else           out <= out;      end    end  endmodule  

The module counter is instantiated with N as 2 even though it is not required because the default value is anyway 2.

DOWN is not passed during module instantiation. And it takes the default value of 0 making it an up-counter.

  module design_top (input clk, input rstn, input en, output [1:0] out);      counter #(.N(2)) u0 (.clk(clk), .rstn(rstn), .en(en));  endmodule  

The default parameters are used to implement the counter where N equals two, making it a 2-bit counter, and DOWN equals zero, making it an up-counter. The output from the counter is left unconnected at the top level.

Verilog Parameters

4-bit down Counter

In this case, the module counter is instantiated with N as 4 making it a 4-bit counter. DOWN is passed a value of 1 during the module instantiation and hence a down-counter is implemented.

  module design_top (input clk, input rstn, input en, output [3:0] out);      counter #(.N(4), .DOWN(1))                  u1 (.clk(clk), .rstn(rstn), .en(en));  endmodule  

Verilog Parameters

Specify Parameters

These parameters are used to provide time and delay values and declared using the specparam keyword. It is allowed to use both within the specified block and the main module body.

  // Use of specify block  Specify  specparam  t_rise = 200, t_fall = 150;  specparam  clk_to_q = 70, d_to_q = 100;  endspecify  // Within main module  module  my_block ( );   specparam  dhold = 2.0;   specparam  ddly  = 1.5;   parameter  WIDTH = 32;  endmodule  

Difference between Specify and Module Parameters

Specify parameter	Module parameter
Specify the specparam keyword declares parameter.	The module parameter is declared by parameter.
It can be declared inside a specific block or within the main module.	It can only be declared within the main module.
This parameter may be assigned specparams and parameters.	This may not be assigned specparams.
SDF can be used to override values.	Instance declaration parameter values or defparam can be used to override.

Notes

Here are some important notes for the Verilog parameters, such as:

If we are using the defparam statement, we must specify a hierarchical path to the parameter.
We cannot skip over a parameter in a module instance parameter value assignment. If we need to do this, use the initial value for a not overwritten parameter.
When one parameter depends on the other, then the second will automatically be updated if we change the first one.

Next TopicVerilog Timing Control

Verilog Parameters

Verilog Parameters

Module parameters

Overriding parameters

Specify Parameters

Difference between Specify and Module Parameters

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