verilog module

Verilog Timing Control Timing control statements are required in simulation to advance time. The time at which procedural statements will get executed…

Verilog Data Types Verilog introduces several new data types. These data types make RTL descriptions easier to write and understand. The data…

Verilog User Defined Primitives A modeling technique whereby the user can virtually argument predefined gate primitives by designing and specifying new primitive…

Design Abstraction Layers The Verilog language would be essential to understand the different layers of abstraction in chip design. The top layer…

Verilog Operators Operators perform an operation on one or more operands within an expression. An expression combines operands with appropriate operators to…

Verilog Tutorial Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a…

Verilog Display Tasks Display system tasks are mainly used to display informational and debug messages to track the simulation flow from log…

Verilog Parameters In Verilog, parameters are constants and do not belong to any other data type such as register or net data…

Verilog Arrays Verilog arrays are used to group elements into multi-dimensional objects to be manipulated more easily. The Verilog does not have…

ASIC Design Flow A typical design flow follows the below structure and can be broken down into multiple steps. Some of these…