Behavioral Modelling and Timing

In Verilog, Behavioral models contain procedural statements, which control the simulation and manipulate variables of the data types.

These statements are contained within the procedures. Each of the procedures has an activity flow associated with it.

During the behavioral model simulation, all the flows defined by the always and initial statements start together at simulation time zero.

The initial statements are executed once, and the always statements are executed repetitively.

Example

The register variables a and b are initialized to binary 1 and 0 respectively at simulation time zero.

The initial statement is completed and not executed again during that simulation run. This initial statement is containing a begin-end block of statements. In this begin-end type block, a is initialized first, followed by b.

  module behave;   reg [1:0]a,b;     initial   begin      a = ‘b1;      b = ‘b0;   end     always   begin      #50 a = ~a;   end     always   begin      #100 b = ~b;   end   End module   

Procedural Assignments

Procedural assignments are for updating integer, reg, time, and memory variables. There is a significant difference between a procedural assignment and continuous assignment, such as:

1. Continuous assignments drive net variables, evaluated, and updated whenever an input operand changes value.

The procedural assignments update the value of register variables under the control of the procedural flow constructs that surround them.

2. The right-hand side of a procedural assignment can be any expression that evaluates to a value. However, part-selects on the right-hand side must have constant indices. The left-hand side indicates the variable that receives the assignment from the right-hand side. The left-hand side of a procedural assignment can take one of the following forms:

Register, integer, real, or time variable: An assignment to the name reference of one of these data types.
Bit-select of a register, integer, real, or time variable: An assignment to a single bit that leaves the other bits untouched.
Part-select of a register, integer, real, or time variable: A part-select of two or more contiguous bits that leave the rest of the bits untouched. For the part-select form, only constant expressions are legal.
Memory element: A single word of memory. Bit-selects and part-selects are illegal on memory element references.
Concatenation of any of the above: A concatenation of any of the previous four forms can be specified, which effectively partitions the result of the right-hand side expression and then assigns the partition parts, in order, to the various parts of the concatenation.

Delay in Assignment

In a delayed assignment, Δt time units pass before the statement is executed, and the left-hand assignment is made. With an intra-assignment delay, the right side is evaluated immediately, but there is a delay of Δt before the result is placed in the left-hand assignment.

If another procedure changes a right-hand side signal during Δt, it does not affect the output. Synthesis tools do not support delays.

Syntax

An assignment has the following syntax, such as:

  Procedural Assignmentvariable = expression  Delayed assignment#Δt variable = expression;  Intra-assignment delayvariable = #Δt expression;  

Blocking Assignments

A blocking procedural assignment statement must be executed before executing the statements that follow it in a sequential block.

The statement does not prevent the execution of statements that follow it in a parallel block.

Syntax

The following syntax is for a blocking procedural assignment, such as:

An lvalue is a data type that is valid for a procedural assignment statement.
= is the assignment operator, and timing control is the optional intra -assignment delay. The timing control delay can either be a delay control or event control. The expression is the right-hand side value the simulator assigns to the left-hand side.
Continuous procedural assignments and continuous assignments also use the = assignment operator used by blocking procedural assignments.

Non-blocking (RTL) Assignments

The non-blocking procedural assignment is used to schedule assignments without blocking the procedural flow.

We can use the non-blocking procedural statement whenever we want to make several register assignments within the same time step without regard to order or dependence upon each other.

Syntax

The following syntax is for a non-blocking procedural assignment:

An lvalue is a data type that is valid for a procedural assignment statement.
<= is the non-blocking assignment operator, and timing control is the optional intra-assignment timing control.
The timing control delay can be either a delay control or event control. The expression is the right-hand side value the simulator assigns to the left-hand side. The non-blocking assignment operator is the same operator the simulator uses for the less-than-or equal relational operator.
The simulator interprets the <= operator as a relational operator when we use it in an expression and interprets the <= operator as an assignment operator when you use it in a non-blocking procedural assignment construct.

When the simulator encounters a non-blocking procedural assignment, the simulator evaluates and executes the non-blocking procedural assignment in two steps:

Step 1: The simulator evaluates the right-hand side and schedules the new value assignment at a time specified by a procedural timing control.

Step 2: At the end of the time step, when the given delay has expired, or the appropriate event has taken place, the simulator executes the assignment by assigning the value to the left-hand side.

Conditions

The conditional statement or if-else statement is used to decide whether a statement is executed.

Syntax

The syntax is as follows:

  <statement>   ::= if ( <expression> ) <statement_or_null>   ||= if ( <expression> ) <statement_or_null>      else <statement_or_null>   <statement_or_null>     ::= <statement>   ||= ;     

The <expression> is evaluated. If it is true (non-zero known value), then the first statement executes. If it is false (zero value or the value is x or z), then the first statement does not execute.
If there is an else statement and <expression> is false, then the else statement executes.
Since the numeric value of the, if expression is tested for being zero, specific shortcuts are possible.

Case Statement

The case statement is a unique multi-way decision statement that tests whether an expression matches several other expressions, and branches accordingly.

The case statement is useful for describing, for example, the decoding of a microprocessor instruction.

Syntax

The case statement has the following syntax:

  <statement>   ::= case ( <expression> ) <case_item>+ endcase   ||= casez ( <expression> ) <case_item>+ endcase   ||= casex ( <expression> ) <case_item>+ endcase   <case_item>   ::= <expression> <,<expression>>* : <statement_or_null>   ||= default : <statement_or_null>   ||= default <statement_or_null>   

The case expressions are evaluated and compared in the exact order in which they are given.
During the linear search, if one of the case item expressions matches the expression in parentheses, then the statement associated with that case item is executed.
If all comparisons fail, and the default item is given, then the default item statement is executed.
If the default statement is not given, and all of the comparisons fail, none of the case item statements are executed.

The case statement differs from the multi-way if-else-if construct in two essential ways, such as:

1. The conditional expressions in the if-else-if construct are more general than comparing one expression with several others, as in the case statement.

2. The case statement provides a definitive result when there are x and z values in an expression.

Looping Statements

There are four types of looping statements. They are used to controlling the execution of a statement zero, one, or more times.

1. Forever continuously executes a statement.

2. Repeat executes a statement a fixed number of times.

3. While executes a statement until expression becomes false, if the expression starts false, the statement is not executed at all.

4. For controls execution of its associated statements by a three-step process are:

Step 1: Executes an assignment normally used to initialize a variable that controls the number of loops executed.

Step 2: Evaluates an expression. Suppose the result is zero, then the for loop exits. And if it is not zero, for loop executes its associated statements and then performs step 3.

Step 3: Executes an assignment normally used to modify the loop control variable’s value, then repeats step 2.

Syntax

The following are the syntax rules for the looping statements, such as:

  <statement>   ::= forever <statement>   ||=forever   begin      <statement>+   end        <Statement>   ::= repeat ( <expression> ) <statement>   ||=repeat ( <expression> )   begin     <statement>+   end        <statement>   ::= while ( <expression> ) <statement>   ||=while ( <expression> )   begin      <statement>+   end        <statement>   ::= for ( <assignment> ; <expression> ; <assignment> )   <statement>   ||=for ( <assignment> ; <expression> ; <assignment> )   begin      <statement>+   end  

Delay Controls

Verilog handles the delay controls in the following ways, such as:

1. Delay Control

The execution of a procedural statement can be delay-controlled by using the following syntax:

  <statement>   ::= <delay_control> <statement_or_null>   <delay_control>   ::= # <NUMBER>   ||= # <identifier>   ||= # ( <mintypmax_expression> )  

The following example delays the execution of the assignment by 10-time units.

Execution of the assignment delays by the amount of simulation time specified by the value of the expression.

2. Event Control

The execution of a procedural statement can be synchronized with a value change on a net or register, or the occurrence of a declared event, by using the following event control syntax:

  <statement>   ::= <event_control> <statement_or_null>     <event_control>   ::= @ <identifier>   ||= @ ( <event_expression> )     <event_expression>   ::= <expression>   ||= posedge <SCALAR_EVENT_EXPRESSION>   ||= negedge <SCALAR_EVENT_EXPRESSION>   ||= <event_expression> <or <event_expression>>   

*<SCALAR_EVENT_EXPRESSION> is an expression that resolves to a one-bit value.

Value changes on nets and registers can be used as events to trigger the execution of a statement. This is known as detecting an implicit event.

Verilog syntax also used to detect change based on the direction of the change, which is toward the value 1 (posedge) or the value 0 (negedge).

The behavior of posedge and negedge for unknown expression values are:

A negedge is detected on the transition from 1 to unknown and from unknown to 0.
And a posedge is detected on the transition from 0 to unknown and from unknown to 1.

Procedures

All procedures in Verilog are specified within one of the following four Blocks.

Initial blocks
Always blocks
Task
Function

Initial Blocks

The initial and always statements are enabled at the beginning of the simulation. The initial blocks execute only once, and its activity dies when the statement has finished.

Syntax

The following syntax is for the initial statement:

Example

The following example illustrates the use of the initial statement for the initialization of variables it the starting of simulation.

  Initial   Begin      Areg = 0; // initialize a register      For (index = 0; index < size; index = index + 1)      Memory [index] = 0; //initialize a memory      Word   End  

Another usage of the initial Blocks is the specification of waveform descriptions that execute once to provide stimulus to the central part of the circuit being simulated.

  Initial   Begin      Inputs = ‘b000000;      // initialize at time zero      #10 inputs = ‘b011001; // first pattern      #10 inputs = ‘b011011; // second pattern      #10 inputs = ‘b011000; // third pattern      #10 inputs = ‘b001000; // last pattern   End   

Always Blocks

The always blocks repeatedly executes. Its activity dies only when the simulation is terminated. There is no limit to the number of initial and always blocks defined in a module.

Syntax

The always statement repeats continuously throughout the whole simulation run. The syntax for the always statement is given below

The always statement is only useful when used in conjunction with some form of timing control because of its looping nature.

Task and Function

Tasks and functions are procedures that are enabled by one or more places in other procedures.

Next TopicVerilog Module

Verilog Behavioral Modelling and Timing

Behavioral Modelling and Timing

Procedural Assignments

Delay in Assignment

Blocking Assignments

Non-blocking (RTL) Assignments

Conditions

Case Statement

Looping Statements

Delay Controls

Procedures

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