Verilog Inter and Intra Delay

Verilog delay statements can have delays specified either on the left-hand side of the assignment operator’s right-hand side.

Inter Assignment Delays

An inter-assignment delay statement has delay value on the left-hand side of the assignment operator.

Inter assignment are those delay statements where the execution of the entire statement or assignment got delayed.

In Verilog, Inter assignment delays often correspond to the inertial delay or the VHDL‘s regular delay statements.

It indicates that the statement itself is executed after the delay expires, and is the most commonly used form of delay control.

Example

  module vd;    reg  a, b, c, q;      initial begin      $monitor(“[%0t] a=%0b b=%0b c=%0b q=%0b”, $time, a, b, c, q);        // Now initialize all signals to 0 at time 0       a <= 0;      b <= 0;      c <= 0;      q <= 0;        // Inter-assignment delay. Wait for #5 time units      // and then assign a and c to 1. Note that ‘a’ and ‘c’      // gets updated at the end of current timestep      #5  a <= 1;      c <= 1;        // Inter-assignment delay. Wait for #5 time units    // and then assign ‘q’ with whatever value RHS gets      // evaluated to      #5 q <= a & b | c;      #20;    end  endmodule  

Here, q becomes 1 at time 10 units because the statement gets evaluated at 10 time units and RHS which is a combination of a, b and c evaluates to 1. After completion the execution, it gives the following output.

xcelium> run  [0] a=0 b=0 c=0 q=0  [5] a=1 b=0 c=1 q=0  [10] a=1 b=0 c=1 q=1  xmsim: *W,RNQUIE: Simulation is complete.

Intra Assignment Delays

Intra assignment delay indicates that the statement itself is executed after the delay expires, and it is the most commonly used form of delay control.

They can be used with blocking and non-blocking assignments. If a statement with intra-assignment timing controls is encountered during simulation, then the expression will be evaluated, and its value will be stored.

Then, the statement’s execution will be suspended until the time specified by the delay control expires. Changes in the expression value up to the time of the event will be ignored.

An intra-assignment delay is declared to the right-hand side of the assignment operator. This indicates that the statement is evaluated, and the values of all signals on RHS are captured first.

Example

  module vd;    reg  a, b, c, q;    initial begin      $monitor(“[%0t] a=%0b b=%0b c=%0b q=%0b”, $time, a, b, c, q);  // Initialize all signals to 0 at time 0      a <= 0;      b <= 0;      c <= 0;      q <= 0;      // Inter-assignment delay: Wait for #5 time units      // and then assign a and c to 1. Note that ‘a’ and ‘c’      // gets updated at the end of current timestep      #5  a <= 1;      c <= 1;      // Intra-assignment delay: First execute the statement      // then wait for 5 time units and then assign the evaluated      // value to q      q <= #5 a & b | c;      #20;    end  endmodule  

The above code gives the below output:

xcelium> run  [0] a=0 b=0 c=0 q=0  [5] a=1 b=0 c=1 q=0  xmsim: *W,RNQUIE: Simulation is complete.

At 5 time units, a and c are assigned using non-blocking statements. And the behavior of non-blocking statements is evaluated but gets assigned to the variable only at the end of the time step.

So the value of a and c is evaluated to 1 but not assigned when the next non-blocking statement q is executed. So when RHS of q is evaluated, a and c still has an old value of 0, and hence $monitor does not detect a change to display the statement.

To observe the change, let us change assignment statements to a and c from non-blocking to blocking.

  // Non-blocking changed to blocking   // rest of the code remains the same           #5  a = 1;  c = 1;      q <= #5 a & b | c;  

And the output looks like as:

xcelium> run  [0] a=0 b=0 c=0 q=0  [5] a=1 b=0 c=1 q=0  [10] a=1 b=0 c=1 q=1  xmsim: *W,RNQUIE: Simulation is complete.

Next TopicVerilog Gate Delay

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Inter Assignment Delays

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