Verilog Priority Encoder
An encoder is a combinational circuit. It has 2^n input lines and n output lines. It takes up these 2^n input data and encodes them into n-bit data. And it produces the binary code equivalent of the input line, which is active high.
But, a normal encoder has a problem. If there is more than one input line with logic value 1, it will encode the wrong output. It only works when only one of the inputs is high. It malfunctions in the case of multiple high inputs.
Thus, to solve the above disadvantage, we “prioritize” the level of each input. Hence, if multiple input lines are selected, the output code will correspond to the input with the highest designated priority. This type of encoder is called the Priority Encoder.
Example
Hardware Schematic
Testbench
A testbench is an HDL module used to test another module, called the device under test (DUT). The test bench contains statements to apply inputs to the DUT and check that the correct outputs are produced.
The input and desired output patterns are called test vectors. Below is the test bench for the priority encoder:
Now, we will see how to design a 4:2 Priority Encoder using different modeling styles in Verilog.
1. Gate Level Modeling
This is virtually the lowest abstraction layer used by designers for implementing the lowest level modules, as the switch level modeling isn’t that common. As the name suggests, gate-level modeling makes use of the gate primitives available in Verilog.
Below we are describing a Priority Encoder using Gate-Level modeling:
From the circuit, we can observe that one AND, two OR and one NOT gates are required for designing. Let’s start coding.
Gate level Modeling for 4:2 priority encoder
As any Verilog code, we start by declaring the module and terminal ports.
Note that we declare outputs first followed by inputs as the built-in gates also follow the same pattern. Let’s declare the input and output ports.
Now, we can declare the intermediate signals. These are signals that are not the terminal ports. From the above circuit, the signals from NOT and AND gates are treated as intermediate signals.
Now we define the logic gates. We use the gate (<outputs>,<inputs>) syntax to use the in-built gates in Verilog.
So, our final code looks like:
2. Dataflow Modeling
In this modeling technique, we use logic equations to describe data flow from input to output. We need not bother about the gates that make up the circuit.
Hence, it is much easier to construct complicated circuits using this abstraction level since there is no need to know the actual physical layout.
It uses the assign keyword to describe the circuit by using the logic equation.
The logic equation for the priority encoder is:
Dataflow modeling of 4:2 Priority Encoder
As always, we start with the module and port declarations:
Now, we have to describe the flow of data to the outputs using assign.
Hence, our final code:
3. Behavioral Modeling
Behavioral Modeling is the highest level of abstraction in Verilog HDL. We can describe the circuit by just knowing how it works. And we do not need to know the logic circuit or logic equation. A truth table is given below, such as:
| Y3 | Y2 | Y1 | Y0 | A1 | A0 |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | X | 0 | 1 |
| 0 | 1 | X | X | 1 | 0 |
| 1 | X | X | X | 1 | 1 |
With this truth table, we can design our priority Encoder using Verilog.
Behavioral Modeling of 4:2 Priority Encoder
let’s starts with the module and the port declaration.
We have to mention output as reg in behavioral modeling. As we use procedural assignments in this modeling style, we have to ensure the outputs retain their value until the next value is given to them.
What we have declared in brackets is the sensitivity list. Here, depending on the value of Y. The always keyword will make sure that the statements get executed every time the sensitivity list is triggered.
In between begin and end, we write the procedure for how the system works:
The case compares an expression to a series of cases and executes the statement or statement group associated with the first matching case. We have used casex, which is a special version of the case. This will treat the x and z values as don’t cares.
4. Structural Modeling
Structural modeling describes the hardware structure of a digital system. It is somewhat similar to gate-level modeling. The only difference is it doesn’t include any built-in gates. We create separate modules for each gate and then integrate to form the whole circuit.
Logic Circuit
In the case of 4:2 priority encoder, we require two OR, an AND and a NOT gates.
Structural Modeling of 4:2 Priority Encoder
To start with code, we will first structurize the OR gate.
We declare the module as or_gate. Then, we declare input and output ports
Then, we use assign statement to write the logical expression for OR.
Thus our OR gate module will be:
Similarly, we do for AND gate:
And NOT gate:
Note: We keep variables for assigning inputs and outputs in one module different from others. It ensures mixing up of signals does not happen during a simulation.
Now we can proceed describing the Priority Encoder as the top-level module.
As usual, start with the module and port declarations.
Now combine these individual modules for logic gates into one single module for the top module. It’s done with the help of a module instantiation concept in which top modules are build using lower modules.
Using the logic circuit, we will instantiate the lower modules in this top using instantiation by port name.
Hence, the Verilog code for the priority encoder in structural style is: