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What is the full form of VHDL

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VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

VHDL is a hardware description language that is used to model the physical hardware used in digital systems like in logic circuits to tell their structure, timing and behavior. It should not be confuse with a programming language as it is not a programming language. There are some predefined data types in VHDL, apart from these a user can also define its own data type.

It was developed by the U.S. Department of Defense in 1981.

Let’s see an image of conversion from VHDL to sysgen block diagram.

Why Use VHDL

• If used in a proper way and structured approach, it will efficiently increase the productivity.
• It gives a benefit to reuse a code according to your use.
• You can move to more advanced tools by using VHDL as electronic tools are developing rapidly.

Disadvantages

• It is hard to learn and implement as it is a big and complex language.
• Tools used in VHDL are comparatively costlier.
• It does not provide all type of technology features.