Top 30+ Most Asked VLSI Interview Questions
Following is the list of most frequently asked VLSI Interview questions and their best possible answers.
1) What do you understand by Boolean logic?
Boolean logic is the foundation of Boolean algebra. It is based and centered on three simple words called Boolean Operators: “Or,” “And,” and “Not”. The core concept of Boolean Logic is based on the idea that all values are either true or false.
2) What is the usage of Boolean logic?
Boolean logic’s based programs are used to make a simple comparison to help decision-making. Boolean logic is a form of Boolean algebra where all values are either true or false. These true and false values are used to test the conditions that finally work as the selection or iteration parameter.
3) How does a Boolean logic control the logical gates?
In Boolean algebra, there are two states for Boolean logic. The true state is denoted by the number one, referred to as logic one or logic high, while the false state represents the number zero, called logic zero or logic low. In digital electronics, the logic “high” is denoted by the presence of a voltage potential.
4) Why do the present VLSI circuits use MOSFETs Instead Of BJTs?
In present VLSI circuits, MOSFETs are preferred over BJTs due to the following reasons:
- MOSFETs are small in size and occupy a minimal silicon area on IC chips as compared to BJTs.
- MOSFETs are relatively simple in terms of manufacturing as compared to BJTs.
- MOSFETs are preferred over BJTs because digital and memory ICs can be implemented with circuits that use only MOSFETs i.e., no resistors, diodes, etc.
5) What are the various regions of operation of MOSFET? How can we use these regions?
There are mainly three regions of operation in MOSFET:
- The cut-off region
- The triode region
- The saturation region
Here, the cut-off region and the triode region are used to operate as a switch, and the saturation region is used to operate as an amplifier.
6) What are the different gates where Boolean logic is used?
There are mainly three types of gates used in Boolean logic:
- NOT Gate: The NOT gate is a logic gate that is used to implement logical negation. It has one input and one output. For example, if A = 0, then the Value of B =1 and vice versa.
- AND Gate: The AND gate is a logic gate that implements logical conjunction. It has one output due to the combination of two outputs. For example, if A and B = 1, then the value of output should be 1. On the other hand, if any input value is 0, then the output will be 0.
- OR Gate: The OR gate is a logic gate that is used to implement logical disjunction. If the value of one or both the inputs to the gate is 1, the output will be 1. If both the inputs are 0, the output will be 0. For example, if A’s value is 1 or B is 0, then the value of output will be 1.
Note: The above are the basic three types of gates where Boolean logic works. Apart from these, there are some other gates that work with the combination of these three basic gates. They are the XNOR gate, NAND gate, NOR gate, and the XOR gate.
7) What do you understand by the threshold voltage?
The threshold voltage is commonly abbreviated as V??. It can be defined as a voltage between Gate and Source, i.e., VGS. A sufficient number of mobile electrons accumulate in the channel region and create a conducting channel. It is the minimum gate-to-source voltage required to create a conducting path between the source and the drain terminals. It is an essential scaling factor to maintain power efficiency.
8) How can binary numbers give a signal or be converted into a digital signal?
Binary number contains two numbers, either 0 or 1. In simple words, we can say that the number 1 represents the ON state, and number 0 represents the OFF state. Using these binary numbers, we can combine billions of machines into one machine or circuit and operate those machines by performing arithmetic calculations and sorting operations.
9) What is the meaning of “the channel is pinched off”?
For a MOSFET, when the voltage value between Gate and Source (VGS) is greater than the threshold voltage (Vt), the channel is induced. As we increase, VDS current starts flowing from Drain to Source till the voltage between gate and channel at the drain end becomes Vt, i.e., VGS – VDS = Vt, the channel depth at Drain end decreases almost to zero. At this stage, the channel is said to be pinched off. In this condition, the MOSFET enters the saturation region.
10) What are the key differences between the TTL chips and CMOS chips?
The list of differences between the TTL chips and CMOS chips:
| TTL Chips | CMOS Chips |
|---|---|
| TTL chip stands for the transistor-transistor logic chip. It uses two bipolar junction transistors in the design of each logic gate. | The CMOS chip stands for Complimentary Metal Oxide Semiconductor chip. It is also an integrated chip, but it uses field-effect transistors in the design. |
| TTL chips utilize BJTs. | CMOS chips utilize FETs. |
| TTLS chip consumes a lot of power, especially at rest. For example, a single gate in a TTL chip consumes approximately 10mW of power. | The CMOS chips consume significantly less power as compared to TTL chips. A single CMOS chip consumes approximately about 10nW of power. |
| TTL chips are generally used in computers. | CMOS chips are generally used in mobile phones. |
| TTL chips can contain a substantial number of parts, such as resistors. | The CMOS chips have a greater density for logic gates. In a CMOS chip, a single logic gate can contain at least two FETs. |
11) What is the most significant advantage of the CMOS chips over the TTL chips?
The most significant advantage of the CMOS chip over the TTL chip is that the CMOS chip has a higher density of logic gates within the same material that improves its efficiency. Another significant advantage is that the CMOS chips consume less power than the power consumed by the TTL chips, even at rest.
12) What do you understand by Channel-length Modulation?
When we increase the VDS beyond the saturation point, it affects the MOSFET characteristics, and the channel pinch-off point starts moving away from the Drain towards the Source. Due to this process, the effective channel length decreases. This phenomenon is called Channel Length Modulation.
13) What do you understand by a sequential circuit?
When a circuit is created by logic gates so that the required logic at the output depends not only on the current input logic conditions but also on the sequences past inputs and outputs, this circuit is called a sequential circuit.
14) What is the depletion region in VLSI?
When we apply a positive voltage across Gates, it causes the free holes (positive charge) to be repelled from the substrate region under the channel region. When these holes are pushed down the substrate, they create a carrier-depletion region.
15) What is Verilog? How is it different from normal programming languages?
Verilog is a Hardware Description Language commonly known as HDL. It is used for describing electronic circuits and systems. In Verilog, the circuit components are prepared inside a module that contains both behavioral and structural statements. The structural statements represent circuit components such as logic gates, counters, and microprocessors, while the behavioral statements represent the programming aspects such as loops, if-then statements, and stimulus vectors.
Verilog is different from normal programming languages in the following aspects:
- Simulation time concept
- Multiple threads
- Basic circuit concepts such as primitive gates and network connections
16) What are the various factors that can affect the threshold voltage?
The threshold voltage (Vt) mainly depends on the voltage connected to the body terminal. It also depends on the temperature. For every 1 degree rise in temperature, the magnitude of threshold voltage decreases by about 2mV.
17) What does the “timescale 1 ns/ 1 ps” specify in Verilog code?
In Verilog code, “the timescale 1 ns/ 1 ps” specifies that the unit of time is 1 ns, and the accuracy/precision will be upto 1ps.
18) What are the two types of procedural blocks in Verilog?
Following are the two types of procedural blocks in Verilog:
- Initial: The initial block runs only once at the time zero.
- Always: The always block loops to execute repeatedly and consistently execute, as the name suggests.
19) What are the main steps required to solve setup and hold violations in VLSI?
Following is the list of steps that we have to perform to solve the setup and hold violations in VLSI:
- The optimization and restructuring of the logic between the flops are necessary to make the logic combined and solve this problem.
- There is a way to modify the flip-flops that offer lesser setup delay and provide faster services to set up a device. Modifying the launch-flop to have a better hold on the clock pin, which provides CK->Q, makes the launch-flop fast and helps fix the setup violations.
- Modify the network of the clock to reduce the delay or slow down the clock that captures the action of the flip-flop.
- There is always added delay/buffer available that allows less delay to the function.
20) What is the reason behind the number of gate inputs to CMOS gates usually limited to four?
The number of gate inputs to CMOS gates usually limited to four because a higher number of stacks make the gate slower. In NOR and NAND gates, the number of gates present in the stack is usually like the number of inputs plus one. That’s why the input gates are restricted to four.
21) What are the different types of skews used in VLSI?
In the clock, a skew is used to reduce the delay or better understand the process. There are mainly three different types of skews used in VLSI.
- Local skew: The local skew is generally used to include the difference between the launching flip-flop and the destination flip-flop. This differentiation helps to define a time path between the two.
- Global skew: The global skew defines the difference between the earliest components reaching the flip flop within the same clock domain. It needs to be mentioned in this skew. The delays are not measured while the clock is uniform for both.
- Useful skew: The useful skew is used to define the delay in capturing flip flop paths, which later helps set up an environment with precise requirements for the launch and capture of the timing path. It needs to be mentioned for design purposes to met the hold requirements.
22) What do you understand by multiplexer?
A multiplexer is a combination circuit that selects one of the many input signals and directs to the only output.
23) What do you understand by an SCR?
SCR is a short form that stands for Silicon Controlled Rectifier. It is a four-layered, 3-terminal solid-state device used to control the flow of current. It is a type of rectifier that is controlled by a logical gate signal.
24) What do you understand by DCMs? Why are they used?
DCM is a short form that stands for Digital Clock Manager. It is a fully digital control system that uses feedback to maintain clock signal characteristics with great precision. A DCM can manage it precisely despite the occurrence of normal variations in operating temperature and voltage.
25) What is slack in VLSI?
A Slack can be defined as a time delay difference from the expected delay to the actual delay in a particular path. It can be negative or positive.
26) What is the usage of defpararm?
The term defparam is a keyword that is used to modify the parameter values at any module instance in the design. The defparam overrides the parameter value at compile time.
27) How many transistors do a static RAM use?
Generally, a static RAM makes use of six transistors. Under the static RAM, read and write operations make use of the same port.
28) What are the different ways to prevent Antenna Violation?
Antenna violation occurs during plasma etching when the charges generated from one metal strip to another accumulate in a single place. The length of the strip is directly proportional to the charges gets accumulated. Therefore, the longer the strip, the more the charges get accumulated.
We can prevent Antenna Violation by using the following methods:
- First, by creating jogging, the metal line consists of at least one metal above the protected layer.
- We have to jog the metal to get the etching effect. This step is taken because if metal gets the etching, the other metal gets disconnected if we don’t take the prevention measures.
- We can also prevent it by adding the reverse diodes at the gates that are used in the circuits.
29) What is the function of tie-high and tie-low cells?
The tie-high and tie-low cells are used to connect the transistors of the gate by using either the power or the ground. The gates are connected using the power or ground to turn off and on them because the power bounces from the ground. The cells stop the bouncing and ease the current from one cell to another. These cells require Vdd that connects to the tie-high cell as a power supply is high, and tie-low gets connected to Vss. After the connection establishment, the transistors function correctly without any ground bounce occurring in any cell.
30) What is the primary function of metastability in VSDL?
Metastability is a phenomenon of unstable equilibrium in digital electronics. In metastability, the sequential element is not able to resolve the state of the input signal. That’s why the output goes into an unresolved state for an unbounded interval of time. Metastability is used in designing a system that violates the setup or holds time requirements. The setup time requirement needs the data to be stable before the clock edge, and the hold time requires the data to be stable after the clock edge has passed. There are potential violations that can lead to setup and hold violations as well.
31) What is the way to stop metastability in VLSI?
The most common way to stop metastability in VLSI is to add one or more successive synchronizing flip-flops to the synchronizer. Using this approach, you can stop metastability for an entire clock period (except for the setup time of the second flip-flop) for metastable events in the first synchronizing flip-flop to resolve them.
32) What is MTBF in VLSI?
MTBF is a short term that stands for Mean Time Between Failure. It is used to provide information on how often a particular element will fail. It also gives the average time interval between two successive failures.
33) What is the difference between the mealy and Moore state machine?
Main differences between the mealy and Moore state machine:
| Moore Machine Model | Mealy Machine Model |
|---|---|
| The Moore model contains the machines that have an entry action, and the output depends only on the machine’s state. | The Mealy model only uses Input Actions, and the output depends on the state and the previous inputs provided during the program. |
| The Moore model is used to design the hardware systems. | The Mealy model is used to design both hardware and software systems. |
| The output of the Moore machine depends only on the state because the program is written in the state only.The output of the Mealy machine depends on the state as well as on the input also. | The output of the Mealy machine is the combination of both input and the state. |
| When we make signal changes, the state variables also have some delay. | The Moore machine doesn’t have glitches, and its output is dependent only on states, not on the input signal level. |
34) What is the difference between Synchronous and Asynchronous Reset?
Main differences between Synchronous and Asynchronous Reset:
| Synchronous Reset | Asynchronous Reset |
|---|---|
| Synchronous reset is the logic that synthesizes to the smaller flip-flops. The clock works as a filter providing the minor reset glitches in this reset, but the glitches occur on the active clock edge. | Asynchronous Reset is also known as reset release or reset removal. In this reset, it is the designer’s responsibility to add the reset to the data paths. |
| Synchronous reset requires an active clock that provides specific clock-cycle-related latency and may impact the timing of the data paths. | Asynchronous reset does not require an active clock to bring flip-flops to a known state. Therefore, it has lower latency than synchronous reset. |