Branch Instruction in AVR microcontroller
To understand the branch instruction, we should know about looping in an AVR microcontroller. After that, we will learn about the branch instructions with two types: Conditional branch instruction and unconditional branch instruction.
Looping in AVR microcontroller
When we write the code, the most fundamental technique which comes to our mind is a loop. The loop can be described as a set of instructions or a repeated operation in terms of programming. There is only one way to execute the loop if we repeatedly write a set of instructions in AVR (Alf and Vegard’s RISC processor).
For example:
With the help of above example, we can see that the above code is taking a lot of space and is also very inefficient. Therefore, we can make the above code of loop simpler and space-efficient with the help of branch instructions.
Branch instruction:
In the program loops and conditionals, the control flow is implemented with the help of branch instruction. If the given condition is satisfied, only then a particular sequence of instruction is executed. When we execute a branch instruction, the execution is switched to a different instruction. The branch instructions are of two types: Conditional branch instruction and unconditional branch instruction.
Conditional Branch instructions
Conditional branch instruction can be described as a set of instructions. It is used to control the program flow with the help of providing a branch out of a loop.
The following table describes the various types of conditional branch instructions and their explanation:
| Instruction | Explanation | Flag Status |
|---|---|---|
| BREQ | BREQ refers to the “Branch if Equal“. It is a type of conditional relative branch. If zero flag (Z) is set, this instruction will test the Z and branches relative to PC (Program counter). Suppose there are two registers D (destination register) and S (source register), containing signed or unsigned binary numbers. The branch will have occurred if the binary number of register D and register S is equal to each other. | Branch if Z = 1 |
| BRNE | BRNE refers to the “Branch if not Equal“. If zero flag (Z) is cleared, this instruction will test the Z and branches relative to PC (Program counter). Suppose there are two registers D (destination register) and S (source register), containing signed or unsigned binary numbers. The branch will have occurred if the binary number of register D and register S is not equal to each other. | Branch if Z = 0 |
| BRSH | BRSH refers to the “Branch if Same or Higher“. If the carry flag (C) is cleared, this instruction will test the C and branches relative to PC (Program counter). Suppose there are two registers D (destination register) and S (source register), containing unsigned binary numbers. The branch will have occurred if the unsigned number of register D is greater than or equal to the unsigned number of register S. | Branch if C = 0 |
| BRLO | BRSH refers to the “Branch if Lower“. If carry flag (C) is set, this instruction will test the C and branches relative to PC (Program counter). Suppose there are two registers D (destination register) and S (source register), containing unsigned binary numbers. The branch will have occurred if the unsigned number of register D is smaller than the unsigned number of register S. | Branch if C = 1 |
| BRLT | BRSH refers to the “Branch if Lower“. If a signed flag (S) is set, this instruction will test the S and branches relative to PC (Program counter). Suppose two registers D (destination register) and S (source register), contain the signed binary numbers. The branch will have occurred if the signed number of register D is less than the signed number of register S. | Branch if S = 1 |
| BRGE | BRGE refers to the “Branch if Greater or Equal“. If the signed flag (S) is cleared, this instruction will test the S and branches relative to PC (Program counter). Suppose two registers D (destination register) and S (source register), contain the signed binary numbers. The branch will have occurred if the signed number of register D is greater than or equal to the signed number of register S. | Branch if S = 0 |
| BRVS | BRVS refers to the “Branch if Overflow set“. If the overflow flag (V) is set, this instruction will test the V and branches relative to PC (Program counter). | Branch if V = 1 |
| BRVC | BRVC refers to the “Branch if Overflow cleared“. If the overflow flag (V) is cleared, this instruction will test the V and branches relative to PC (Program counter). | Branch if V = 0 |
Loop using BRNE
The BRNE refers to the branch if not equal. If Z is cleared, it will test the zero flag (Z) and branches relatively to PC. It basically uses the Z flag in a status register.
For example:
In this example, we will write a code to add 5 to C, and this process will be repeated 20 times. Lastly, with the help of BRNE instruction, we will send the sum to PORTC.
All of the conditional branches basically use short jumps. This means that the target address must be within 64 bytes of the program counter.
Unconditional Branch Instruction
The unconditional branching can be described as the jump where the control is transferred to the target address unconditionally. The AVR basically has three types of unconditional branch instructions, i.e., JMP, IJMP, and RJMP. The instructions of an unconditional branch are described as follows:
JMP:
JMP instructions are also known as long jump. It is a type of unconditional jump that can go to any memory location, but that location must be within the 4M(word) address space of AVR. The JMP instruction is the 4-byte instruction. With the help of 10 bits, the opcode is represented, and with the help of rest of the bits means 22 bits, the 22-bit address of the target location is represented.
RJMP:
RJMP instructions are also known as the relative jump. RJMP instructions are the 2-byte instruction. With the help of first four bits, the opcode is represented, and with the help of rest of bits, the relative address of a target location is represented. The range of relative address is 000-$FFF, which is divided into two jumps: backward jumps and forward jumps. This jump must be within -2048 and +2047 of memory, which is relative to the current program counter address.
IJMP:
IJMP instructions are also known as the indirect jump. The IJMP instructions are the 2-byte instruction. When we execute the IJMP instruction, the program counter will be loaded with the help of Z register’s content. That means the Z register provides an address, and IJMP jumps to this address. This instruction is able to jump within the lowest 64k words (128KB) of the PC (program counter).